The present invention relates generally to test methods used in integrated circuit manufacturing. More particularly, the present invention relates to test methods for determining a value of barrier permeability associated with a test barrier at a via bottom based on a measured lifetime of a test structure containing the test barrier.
As interconnect dimensions scale to smaller sizes and current densities increase in today""s integrated circuits, the reliability of interconnects becomes a greater concern due to increased electromigration rates. Electromigration (EM), which is the diffusion of atoms in an interconnect induced by an electric current, can lead to interconnect failure by voiding or extrusion at sites of atomic flux divergence, that is, where the net flux of atoms is not zero. The net displacement of atoms during EM causes local stress changes in the interconnect in which either tensile or compressive stresses develop as atoms are depleted or accumulated, respectively. Tensile and compressive stresses can develop, for example, at the electron-source (cathode) and the electron-sink (anode) vias, respectively, when the vias arc no-flux boundaries, such as W- or Ti-filled vias. Failure of the interconnect will occur, for example, once the stress somewhere in the line exceeds a critical stress required for void nucleation.
One of the purposes of a barrier layer is to prevent mass flow (diffusion of atoms) between the metal layers and the resultant interconnect failures due to electromigration. As device sizes continue to shrink, barrier materials must become thinner in order to minimize resistance at the vias. However, the thinning of the barrier may cause the interface of the via/feeder-line to become permeable to mass flux and lead to EM failures.
FIG. 1A illustrates a cross-sectional view of a two metal layer interconnect structure 100 having a first conductor 105, a second conductor 110, a third conductor 115, respectively. A barrier layer 120 is disposed between the first conductor 105 and the second conductor 110 at a cathode via 125 and disposed between the second conductor 110 and the third conductor 115 at an anode via 130. The second conductor 110, having a length L 135, forms an interconnect between the first and third conductors. Length L 135, is measured from the via at one end of the interconnect line to the via at the other end. FIG. 1A also illustrates the tensile stresses 140 which can develop in the region of the cathode via 125, and the compressive forces 145 which can develop in the region of the anode via 130 as electrons flow from the cathode to the anode. Typically, the layers may be formed, for example, using conductors of Al, Al alloy, with a TiN barrier layer, or using Cu conductors, with a TaN barrier layer.
FIG. 1B shows a cross-sectional view of another two metal layer interconnect structure 150 similar to the structure 100 illustrated in FIG. 1A. FIG. 1B illustrates a common failure mode due to voids 160 which typically form in areas of the highest tensile stresses (e.g., 140 of FIG. 1A), near the region of the cathode via 125. Mass flux-divergence taking place at the electron-source (cathode) vias, produces maximum tensile stresses in this region. When these tensile forces reach a critical stress level, void nucleation occurs. Eventually, if a high enough current density is maintained through the interconnect, failure of the interconnect may result due to electromigration (EM failure).
FIGS. 1A and 1B also illustrate the conventional EM test structures which attempt to determine the lifetime of such structures, to analyze the effects of EM on various structures, or the effect of a barrier layer on EM. In the conventional method, current is conducted from the cathode conductor to the anode conductor until the resistance of the test structure reaches a predetermined failure criterion. Conventional methods measure the lifetime of the test structure, or may even indicate improved or worsened lifetimes, but do not quantify a specific barrier parameter associated with the structure""s lifetime.
In addition, conventional two-level EM test structures often have feeder lines that are much wider than the test line and therefore are insensitive to the permeability of the barrier at the via since mass flow from the feeder line to the via is negligible when compared to the volume of the feeder line.
Currently, some conventional EM test structures rely on an assumption that a barrier layer being tested has no mass flux entering from the cathode/feeder line, but may in fact, have a mass flux which may reduce or invalidate the effectiveness of testing lifetime measurements associated with specific parameters of the barrier which are under investigation.
Accordingly, there is a need for quantifying a specific barrier layer parameter associated with the lifetime of a test structure during electromigration in a test structure.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a method of determining a barrier permeability, wherein a barrier permeability value is assigned to a test barrier based on a measured lifetime of a test structure used in integrated circuit manufacturing.
In the present invention a new EM test structure is also proposed in order to not only detect the permeability of a barrier/via, but also to allow for the quantifying of the degree of permeability, herein symbolized as (xcex1). According to one aspect of the invention, this may be accomplished using experimental lifetimes from different barrier permeability structures and by EM simulation.
In one aspect of the present invention, an interconnect test structure is formed for determining a magnitude of electromigration permeability of a layer material within an interconnect. The interconnect test structure includes a test line comprised of a conductive material and having a first current density, J1, and a first length, L1. The interconnect test structure also includes a feeder line comprised of a conductive material and coupled to the test line, and the feeder line is a source of electrons flowing into the test line. Furthermore, the interconnect test structure includes a supply line comprised of a conductive material and coupled to the test line and having a second current density, J2, and a second length, L2, and the supply line is a sink of electrons flowing from the test line. In addition, a no-flux structure is disposed between the feeder line and the test line, and the layer material is disposed between the test line and the supply line.
Additionally, a product of the first current density and the first length of the test line, J1*L1, is less than a critical Blech length constant, (J*L)CRIT, and a product of the second current density and the second length of the supply line, J2*L2, is less than the critical Blech length constant, (J*L)CRIT, to ensure that the test line and the supply line are individually immortal such that electromigration failure of the interconnect test structure is attributable to permeability of the layer material. On the other hand, a net current density and length product (J*L)NET for the test line and the supply line is greater than the critical Blech length constant, (J*L)CRIT, to ensure that the interconnect test structure exhibits electromigration failure from permeability of the layer material.
In another aspect of the present invention, in a system and method for determining the magnitude of electromigration permeability of the layer material within the test interconnect structure, a current source is operable to conduct current through the interconnect test structure with electrons flowing from the feeder line through the test line to the supply line. Furthermore, a timer is operable to measure an electromigration lifetime of the interconnect test structure, and a processor determines the magnitude of electromigration permeability of the layer material from the measured electromigration lifetime of the interconnect test structure.
The aspects of the invention find application in devices which include semiconductors, integrated circuits, and the manufacturing of such devices.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.